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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adp1147-3.3/adp1147-5 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 high efficiency step-down switching regulator controllers functional block diagram q r s v in sense(C) v th2 sleep v os 1.25v off-time control 5pf 100k v 13k v v in p-drive ground sense(+) sense(C) c t i th shutdown adp1147 10mv to 150mv r s q 1 2 c v g s t b v th1 reference features greater than 95% efficiency current mode switching architecture provides superior load and line transient response wide input voltage range 3.5 v* to 16 v user defined current limit short circuit protection shutdown pin low dropout voltage low standby current 160 m a typ low cost available in 8-lead pdip or 8-lead soic applications portable computers modems cellular telephones portable equipment gps systems handheld instruments general description the adp1147 is part of a family of high efficiency step-down switching regulators. these regulators offer superior load and line transient response, a user defined current limit and an automatic power savings mode. the automatic power savings mode is used to maintain efficiency at lower output currents. the adp1147 incorporates a constant off-time , current mode switching architecture to drive an external p-channel mosfet at frequencies up to 250 khz . constant off-time switching gen- erates a constant ripple current in the external inductor. this results in a wider input voltage operating range of 3.5 v* to 16 v, and a less complex circuit design. * 3.5 volt operation is for the adp1147-3.3. 1000pf shutdown l * 50 m h d1 30bq040 1 m f 0v = normal 1.5v = shutdown r sense ** 0.05 v r c 1k v c c 3300pf c t 470pf v in (5.2v to 12v) c in 100 m f v out 5v/2a c out 390 m f p-channel irf7204 shutdown gnd p-drive sense(C) adp1147 i th c t v in sense(+) + + + *coiltronics ctx 50C2mp **krl sl-1-c1-0r050j figure 1. high efficiency step-down converter (typical application) a very low dropout voltage with excellent output regulation can be obtained by minimizing the dc resistance of the inductor, the r sense resistor, and the r ds(on) of the p-mosfet. the power savings mode conserves power by reducing switching losses at lower output currents. when the output load current falls below the minimum required for the continuous mode the adp1147 will automatically switch to the power savings mode. it will remain in this mode until the inductor requires additional current or the sleep mode is entered. in sleep mode with no load the standby power consumption of the device is reduced to 2.0 mw typical at v in = 10 v. for designs requiring even greater efficiencies refer to the adp1148 data sheet. load current C ma 100 95 60 1 10k 10 100 1k 90 85 65 80 75 70 v in = 6 volts v in = 10 volts efficiency C % figure 2. adp1147-5 typical efficiency, figure 1 circuit
C2C rev. 0 adp1147-3.3/adp1147-5Cspecifications electrical characteristics adp1147 parameter conditions v s min typ max units regulated output voltage v in = 9 v v out adp1147-3-3 i load = 700 ma 3.23 3.33 3.43 v adp1147-5 i load = 700 ma 4.90 5.05 5.20 v output voltage line regulation t a = +25 c d v out v in = 7 v to 12 v, i load = 50 ma C40 0 +40 mv output voltage load regulation adp1147-3.3 5 ma < i load < 2 a d v out 40 65 mv adp1147-5 5 ma < i load < 2 a 60 100 mv sleep mode output ripple t a = +25 c, i load = 0 a 50 mv p-p input dc supply current 2 t a = +25 c normal mode 4 v < v in < 16 v i q 1.6 2.3 ma sleep mode (adp1147-3.3) 4 v < v in < 16 v 160 250 m a sleep mode (adp1147-5) 4 v < v in < 16 v 160 250 m a shutdown v shutdown = 2.1 v, 4 v < v in < 16 v 10 22 m a current sense threshold voltage adp1147-3.3 v sense (C) = v out + 100 mv ( forced ) t a = +25 c10mv v sense (C) = v out C 100 mv ( forced )v 5 Cv 4 120 150 170 mv adp1147-5 v sense (C) = v out + 100 mv ( forced ) t a = +25 c10mv v sense (C) = v out C 100 mv ( forced ) 120 150 170 mv shutdown pin threshold t a = +25 cv 6 0.6 0.8 2 v shutdown pin input current 0 v < v shutdown < 8 v, v in = 16 v i 6 1.2 5 m a t a = +25 c c t pin discharge current t a = +25 c, v out in regulation, 50 70 90 m a v sense (C) = v out, v out = 0 v i 2 210 m a off-time c t = 390 pf, i load = 700 ma t off 456 m s driver output transition times t a = +25 c c l = 3000 pf (pin 8) v in = 6 v tr, tf 100 200 ns notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 dynamic supply current is higher due to the gate charge being delivered at the switching frequency. specifications subject to change without notice. (0 8 c t a +70 8 c 1 , v in = 10 v, v shutdown = 0 v unless otherwise noted) absolute maximum ratings input supply voltage (pin 1) . . . . . . . . . . . . . . 16 v to C0.3 v continuous output current (pin 8) . . . . . . . . . . . . . . 50 ma sense voltages (pins 4, 5) . . . . . . . . . . . . . . . . 10 v to C0.3 v operating ambient temperature range . . . . . 0 c to +70 c extended commercial temperature range . . C40 c to +85 c junction temperature* . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . +300 c *t j is calculated from the ambient temperature, t a, and power dissipation, p d , according to the following formulas: adp1147an-3.3, adp1147an-5: t j = t a + (p d 110 c/w). adp1147ar-3.3, adp1147ar-5: t j = t a +(p d 150 c/w). ordering guide output package package model voltage description option adp1147an-3.3 3.3 v plastic dip n-8 adp1147ar-3.3 3.3 v soic so-8 adp1147an-5 5 v plastic dip n-8 adp1147ar-5 5 v soic so-8
C3C rev. 0 adp1147-3.3/adp1147-5 electrical characteristics adp1147 parameter conditions v s min typ max units regulated output voltage v in = 9 v adp1147-3.3 i load = 700 ma v out 3.17 3.33 3.4 v adp1147-5 i load = 700 ma 4.85 5.05 5.2 v input dc supply current normal mode 4 v < v in < 16 v i q 1.6 2.6 ma sleep mode (adp1147-3.3) 4 v < v in < 16 v 160 280 m a sleep mode (adp1147-5) 5 v < v in < 16 v 160 280 m a shutdown v shutdown = 2.1 v, 4 v < v in < 16 v 10 28 m a current sense threshold voltage adp1147-3.3 v sense (C) = v out + 100 mv (forced) v 5 Cv 4 t a = +25 c25mv v sense (C) = v out C 100 mv ( forced ) 120 150 175 mv adp1147-5 v sense (C) = v out + 100 mv ( forced ) t a = +25 c25mv v sense (C) = v out C 100 mv ( forced ) 120 150 175 mv shutdown pin threshold v 6 0.55 0.8 2 v off-time c t = 390 pf, i load = 700 ma t off 3.8 5 6 m s notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. specifications subject to change without notice. pin function descriptions pin no. mnemonic function 1v in input voltage. 2c t external capacitor connection. this capacitor sets the operating frequency of the device. the frequency is also dependent on the input voltage level. 3i th error amplifier decoupling pin. pin 3 voltage level causes the comparator current threshold to increase. 4 sense(C) this connects to internal resistive divider, which senses the output voltage. pin 4 is also the (C) input for the current comparator. 5 sense(+) this provides the + input to the current comparator. the offset between pins 4 and 5 together with r sense establish the current trip threshold. 6 shutdown when this pin is pulled high, it keeps the mosfet turned off. when the pin is pulled to ground, the adp1147 functions normally. this pin cannot be left floating. 7 gnd independent ground lines must be connected separately to (a) the negative pin of c out and (b) the cathode of the schottky diode and the negative terminal of c in . 8 p-drive provides high current drive for the mosfet. voltage swing is from v in to ground at this pin. (C40 8 c t a +85 8 c 1 , v in = 10 v, unless otherwise noted) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp1147 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations 8-lead plastic dip (n-8) 1 2 3 4 8 7 6 5 top view (not to scale) adp1147 t jmax = 125 8 c, u ja = 110 8 c/w v in sense+ shutdown gnd p-drive c t i th senseC 8-lead soic (so-8) 1 2 3 4 8 7 6 5 top view (not to scale) adp1147 t jmax = 125 8 c, u ja = 150 8 c/w v in sense+ shutdown gnd p-drive c t i th senseC warning! esd sensitive device
adp1147-3.3/adp1147-5 C4C rev. 0 Cperformance characteristics maximum output current C amps 200 0 05 1234 150 100 50 r sense C m v figure 3. selecting r sense vs. maximum output current i out C amps efficiency C % 100 95 80 10m 30m 3 0.1 0.3 1 90 85 i 2 r gate charge adp1147 i q schottky diode figure 6. typical efficiency losses load current C ma output voltage C v 5.11 5.10 5.02 0 400 2000 800 1200 1600 5.06 5.05 5.04 5.03 5.09 5.07 5.08 figure 1 circuit v in = 6 volts v in = 12 volts figure 9. load regulation frequency C khz capacitance C pf 1000 0 600 400 200 800 0 300 100 200 v sense = v out = +5v v in = +12v v in = +10v v in = +7v figure 4. operating frequency vs. timing capacitor input voltage C volts efficiency C % 100 95 70 58 20 11 14 17 90 85 80 75 figure 1 circuit 1 amp 0.1 amp figure 7. efficiency vs. input voltage input voltage C volts supply current C ma 1.6 0 46 20 8 1012141618 1.4 0.8 0.6 0.4 0.2 1.2 1.0 active mode sleep mode figure 10. dc supply current (v in C v out ) voltage C volts 1000 800 0 05 1 234 600 400 200 l = 50 m h r sense = 0.02 v l = 25 m h r sense = 0.02 v l = 50 m h r sense = 0.05 v c out C m f figure 5. sele cting minimum output capacitor vs. (v in C v out ) and inductor input voltage C v output voltage C v 5.11 5.10 5.03 48 16 12 5.07 5.06 5.04 5.05 5.09 5.08 100ma 1 amp 300ma figure 1 circuit figure 8. adp1147-5 output voltage vs. input voltage input voltage C volts supply current C m a 40 0 46 20 8 1012141618 35 20 15 10 5 30 25 v shutdown = +2v figure 11. supply current in shutdown
adp1147-3.3/adp1147-5 C5C rev. 0 (v in C v out ) C volts 12 12 46810 normalized frequency 1.8 1.6 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 +70c +25c 0c figure 12. operating frequency vs. (v in Cv out ) temperature C 8 c sense voltage C mv 155 150 130 0 25 100 70 85 145 140 135 maximum threshold figure 15. current sense threshold voltage operating frequency C khz gate charge current C ma 30 0 20 50 260 80 110 140 170 200 230 25 20 15 10 5 q n + q p = 50nc q n + q p = 100nc figure 13. gate charge supply current input voltage C volts efficiency C % 95 90 70 58 20 11 14 17 85 80 75 1 amp 0.1 amp figure 16. efficiency vs. input voltage at v o = 3.3 v; figure 1 circuit with adp1147-3.3 +3.3v +5v output voltage C volts 80 30 0 0.3 0.5 5 1 1.5 2 2.5 3 3.3 3.5 4 4.5 70 40 20 10 60 50 off-time C m s figure 14. off-time vs. v out input voltage C volts output voltage C v 3.35 3.34 3.27 48 16 12 3.31 3.30 3.28 3.29 3.33 3.32 300ma 100ma 1 amp figure 17. output voltage vs. input voltage (v o = 3.3 v); figure 1 circuit with adp1147-3.3 load current C ma output voltage C v 3.36 3.34 3.18 0 400 2000 800 1200 1600 3.26 3.24 3.22 3.20 3.32 3.28 3.30 v in = 6 volts v in = 12 volts figure 18. load regulation (v o = 3.3 v); figure 1 circuit with adp1147-3.3
adp1147-3.3/adp1147-5 C6C rev. 0 3.3v 0v (a) continuous mode operation 3.3v 0v (b) power saving mode figure 19. c t waveforms 1000pf shutdown p-drive sense(+) sense(C) adp1147-3.3 i th c t v in 1 m f r sense v out 1k v 3300pf c t 390pf v in ground c in d1 p-channel l shutdown c out ground plane figure 20. circuit diagram indicating the recommended ground plane scheme for pcb layout 1 2 3 4 u1 adp1147-5 p-drv snsC i th c t v in gnd shd sns+ r3 100 v r4 100 v r2 0.02 v v out 5v/3a c7 2.2nf c9Cc11 220 m f 3 10v os-con + r1 1k v c6 3.3nf c5 470pf l1 50 m h + c1 1 m f d3 1n4148 r5 20k v r6 470 v q1 2n3906 q2 2n2222 r7 220 v q4 irf7403 q3 vn2222ll d2 30bq040 + c2-c4 220 m f/16v os-con c8 1 m f d1 1n4148 v in 6v to 14v 8 7 6 5 figure 21. 5 v/3 a regulator using n-channel device irf7204 l* 50 m h 1nf shutdown gnd p-drive sense(+) sense(C) adp1147-3.3 i th c t v in 1 m f r sense** 50m v v out 3.3v/2a r c 1k v 3300pf c t 620pf v in 4vC14v d1 30bq040 shutdown c out 220 m f 6.3v x2 c in 100 m f 25v *coiltronics ctx50-4 **krl sl-1-c1-0r050j figure 22. 3.3 v/2 a regulator load current C ma 100 95 60 1 10k 10 efficiency C % 100 1k 80 75 70 65 90 85 v in = 6 volts v in = 10 volts figure 23. efficiency vs. load current at v o = 3.3 v; figure 22 circuit
adp1147-3.3/adp1147-5 C7C rev. 0 applications the adp1147 family of regulators incorporate a current mode, constant off-time architecture to switch an external p-channel mosfet. the external mosfet can be switched at frequen- cies up to 250 khz. the switching frequency of the device is determined by the value selected for capacitor c t . a regulated output voltage is maintained by the feedback volt- age at the sense(C) pin. the sense(C) pin is connected to an internal voltage divider. the voltage from this internal divider is fed to comparator v, and gain block g. it is then compared to an internal 1.25 volt reference. the adp1147 is capable of maintaining high levels of efficiency by automatically switching between the power saving and con- tinuous modes. the internal r-s flip-flop #2 controls the device in the power saving mode, and gain block g assumes control when the device is in the continuous mode of operation. during the p-mosfet on time, the voltage developed across r sense is monitored by the sense(C) and sense(+) pins of the device. when this voltage reaches the threshold level of comparator c the output trips, switching the p drive to v in , and turns the external p-mosfet off. at this point capacitor c t begins to discharge at a rate that is determined by the off-time controller. the c t discharge current is proportional to the voltage measured at the sense(C) pin. when the voltage on cap c t decays to the threshold voltage (v th1 ), comparator t switches and sets r-s flip-flop #1. this forces the p-drive out- put low, and turns on the p-mosfet. the sequence is then repeated. as the load current is increased, the output voltage starts to drop. this causes the gain circuit to raise the threshold of the current comparator, and the load current is now tracked. when load currents are low, comparator b sets the r-s flip-flop #2 and asserts the power savings mode of operation. compara- tor b monitors the voltage developed across r sense . as the load current decreases to 50% of the designed inductor ripple cur- rent, the voltage reverses polarity. this reversal causes compara- tor b to trip, setting the q-bar output of r-s flip-flop #2 to a logic zero, and interrupts the cycle by cycle operation of the output. the output storage capacitors are then slowly discharged by the load. when the output cap voltage decays to the v os level of comparator v, it resets flip-flop #2, and the normal cycle by cycle mode of operation resumes. if load currents are extremely small, the time it takes for flip-flop #2 to reset increases. during the extended wait for reset period, capacitor c t will discharge below the value of v th2 causing comparator s to trip. this forces the internal sleep bar low and the device enters the sleep mode. a significant amount of the ic is disabled during the sleep mode, reducing the ground current from 1.6 ma to 160 m a, typical. in sleep mode the p-mosfet is turned off until additional inductor current is required. the sleep mode is terminated when flip-flop #2 is reset. due to the constant off-time architecture, the input voltage has an effect on the device switching frequency. to limit the effects of this variation in frequency the discharge current is increased as the device approaches the dropout voltage of v in +1.5 v. in the dropout mode the p-mosfet is constantly turned on. determining the output current and the value for r sense the value selected for r sense is determined by the required output current. the current comparator c has a threshold volt- age range of 10 mv/r sense to 150 mv/r sense maximum. this threshold sets the peak current in the external inductor and yields a maximum output current of: i max = i peak i ripple p - p 2 the resistance values for r sense can range from 20 m w to 200 m w . a graph for selecting r sense vs. the maximum out- put current is shown in figure 3. the value of r sense can be determined by using the following equation: r sense ( in m w ) = 100/ i max this equation allows for a design margin due to component variations. the following equations are used to approximate the trip point for the power savings mode and the peak short circuit current. i power savings ~ 5 mv/r sense + v o t off /2l i sc(pk) = 150 mv/r sense the adp1147 automatically increases the t off time when a short circuit condition is encountered. this allows sufficient time for the inductor to decay between switching cycles. due to the resulting inductor ripple current the average short circuit current i sc(avg) is reduced to approximately i max . determining the operating frequency and selecting values for c t and l the adp1147 incorporates a constant off-time architecture to switch an external p-mosfet. the off-time (t off ) is deter- mined by the value of the external timing cap c t . when the p-mosfet is turned on the voltage across c t is charged to approximately 3.3 volts. during the switch off-time the voltage on c t is discharged by a current that is proportional to the voltage level of v out . the voltage across c t is representative of the current in the inductor, which decays at a rate that is pro- portional to v out . due to this relationship the value of the inductor must track the value selected for c t . the following equation is used to determine the desired con- tinuous mode operating frequency: c t = 1 - v out + v d v in + v d 1. 3 10 4 f v d = the voltage drop across the schottky diode. the graph in figure 4 can be used to help determine the capaci- tance value of c t vs. the operating frequency and input voltage. the p-mosfet gate charge losses increase with the operating frequency and results in lower efficiency (see the efficiency section).
adp1147-3.3/adp1147-5 C8C rev. 0 the formula used to calculate the continuous operating fre- quency is: f = 1 - v out + v d v in + v d t off t off = 1. 3 10 4 c t v reg v out v reg is the value of the desired output voltage. v out is the ac- tual measured value of the output voltage. when in regulation v reg /v out is equal to 1. the switching frequency of the adp1147 decreases as the input voltage decreases. the adp1147 will reduce the t off time by increasing the discharge current in ca- pacitor c t if the input to output voltage differential falls below 1.5 volts. this is to eliminate the possible occurrence of audible switching prior to dropout. now that the operating frequency has been determined and the value selected for c t , the required inductance for inductor l can be computed. the inductor l should be chosen so it will generate no more than 25 mv/r sense of peak-to-peak inductor ripple current. the following equation is used to determine the required value for inductor l: 25 mv r sense = ( v out + v d ) t off l min or l min = ( v out + v d ) t off r sense 25 mv substituting for t off above gives the minimum required induc- tor value of: l min = 5.1 10 5 r sense c t v reg the esr requirements for the output storage capacitor can be relaxed by increasing the inductor value, but efficiency due to copper losses will be reduced. conversely, the use of too low an inductance may allow the inductor current to become discon- tinuous, causing the device to enter the power savings mode prematurely. as a result of this the power savings threshold is lowered and the efficiency at lower current levels is severely reduced. inductor core considerations now that the minimum inductance value for l has been deter- mined, the inductor core selection can be made. high efficiency converters generally cannot afford the core losses found in low cost powdered iron cores. this forces the use of a more expen- sive ferrite, molypermalloy, or kool mu ? cores. the typical efficiency in figure 1 reflects the use of a molypermalloy core. the cost of the inductor can be cut in half by using a kool mu core type ctx 50-4 by coiltronics, but the efficiency will be approximately 1%C2% less. the actual core losses are not de- pendent on the size of the core, but on the amount of induc- tance. an increase in inductance will yield a decrease in the amount of core loss. although this appears to be desirable, more inductance requires more turns of wire with added resistance and greater copper losses. kool mu is a registered trademark of magnetics, inc. using a ferrite cores in a design can produce very low core losses, allowing the designer to focus on minimizing copper loss and core saturation problems. ferrite cores exhibit a condition known as hard saturation, which results in an abrupt collapse of the inductance when the peak design current is exceeded. this causes the inductor ripple current to rise sharply, the out- put ripple voltage to increase and the power savings mode of operation to be erroneously activated. to prevent this from occurring the core should never be allowed to saturate. molypermalloy (from magnetics, inc.) is a very good, low loss core material for a toroids, but is more expensive than a ferrite core. a reasonable compromise between price and performance, from the same manufacturer is kool mu. toroidal cores are extremely desirable where efficient use of available space and several layers of wire are required. they are available in various surface mount configurations from coiltronics inc. and other companies. power mosfet selection and considerations the adp1147 requires the use of an external p-channel mosfet. the major parameters to be considered when select- ing the power mosfet are the threshold voltage v gs(th) and the on resistance of the device r ds(on) . the minimum input voltage determines if the design requires a logic level or a standard threshold mosfet. in applications where the input voltage is > 8 volts, a standard threshold mosfet with a v gs(th) of < 4 volts can be used. in designs where v in is < 8 volts, a logic level mosfet with a v gs(th) of < 2.5 volts is recommended. note: if a logic level mosfet is selected, the supply voltage to the adp1147 must not exceed the absolute maximum for the v gs of the mosfet (e.g., < 8 volts for irf7304). the r ds(on) requirement for the selected power mosfet is determined by the maximum output current (i max ). an as- sumption is made that when the adp1147 is operating in the continuous mode, either the schottky diode or the mosfet are al ways conducting the average load current. the following formulas are used to determine the duty cycle of each of the components. p - channel mosfet duty cycle = v out + v d v in + v d schottky diode duty cycle = v in v d v in + v d once the duty cycle is known, the r ds(on) requirement for the power mosfet can be determined by: r ds ( on ) = ( v in + v d ) p p ( v out + v d ) i max 2 (1 +d p ) where p p is the max allowable power dissipation and where d p is the temperature dependency of r ds(on) for the mosfet. effi- ciency and thermal requirements will determine the value of p p , (refer to efficiency section). mosfets usually specify the 1+ d as a normalized r ds(on ) vs. temperature trace, and d can be approximated to 0.007/ c for most low voltage mosfets. output diode considerations when selecting the output diode careful consideration should be given to peak current and average power dissipation so the maximum specifications for the diode are not exceeded.
adp1147-3.3/adp1147-5 C9C rev. 0 the schottky diode is in conduction during the mosfet off- time. a short circuit of v out = 0 is the most demanding situa- tion on for the diode. during this time it must be capable of delivering i sc(pk) for duty cycles approaching 100%. the equa- tion below is used to calculate the average current conducted by the diode under normal load conditions. i d 1 = v in v out v in + v d i load to guard against increased power dissipation due to undesired ringing, it is extremely important to adhere to the following: 1. use proper grounding techniques. 2. keep all track lengths as short as possible, especially connec- tions made to the diode (refer to pcb layout considerations section). the allowable forward voltage drop of the diode is determined by the maximum short circuit current and power dissipation. the equation below is used to calculate v f : v f = p d /i sc(pk) where p d is the maximum allowable power dissipation and is determined by the system efficiency and thermal requirements (refer to efficiency section). c in considerations during the continuous mode of operation the current drawn from the source is a square wave with a duty cycle equal to v out /v in . to reduce or prevent large voltage transients an input capacitor with a low esr value and capable of handling the maximum rms current should be selected. the formula below is used to determine the required maximum rms capacitor current: c in i rms = [ v out ( v in Cv out )] 0.5 i max / v in the maximum for this formula is reached when v in = 2 v out , where i rms = i out /2. it is best to use this worst case scenario for design margin. manufacturers of capacitors typically base the current ratings of their caps on a 2000-hour life. this requires a prudent designer to use capacitors that are derated or rated at a higher temperature. the use of multiple capacitors in parallel may also be used to meet design requirements. the capacitor manufacturer should be consulted for questions regarding spe- cific capacitor selection. in addition, for high frequency decoupling a 0.1 m f to 1.0 m f ceramic capacitor should be placed and connected as close to the v in pin as possible. c out considerations the minimum required esr value is the primary consideration when selecting c out . for proper circuit operation the esr value of c out must be less than two times the value selected for r sense (see equation below): c out minimum required esr < 2 r sense when selecting a capacitor for c out , the minimum required esr is the primary concern. proper circuit operation mandates that the esr value of c out must be less than two times the value of r sense . a capacitor with an esr value equal to r sense will provide the best overall efficiency. if the esr value of c out increases to two times r sense a 1% decrease in efficiency results. united chemicon, nichicon and sprague are three manufacturers of high grade capacitors. sprague offers a capacitor that uses an os-con semiconductor dielectric. this style capacitor pro- vides the lowest amount of esr for its size, but at a higher cost. most capacitors that meet the esr requirements for i p-p ripple will usually meet or exceed the rms current requirements. the specifications for the selected capacitor should be consulted. surface mount applications may require the use of multiple capacitors in parallel to meet the esr or rms current require- ments. if dry tantalum capacitors are used it is critical that they be surge tested and recommended by the manufacturer for use in switching power supplies such as type 593d from sprague. avx offers the tps series of capacitors with various heights from 2 mm to 4 mm. the manufacturer should be consulted for the latest information, specifications and recommendations concerning specific capacitors. when operating with low supply voltages, a minimum output capacitance will be required to prevent the device from operating in a low frequency mode (see figure 5). the output ripple also increases at low frequencies if c out is too small. transient response the response of the regulator loop can be verified by monitoring the transient load response. several cycles may be required for a switching regulator circuit to respond to a step change in the dc load current (resistive load). when a step in the load current takes place a change in v out occurs. the amount of the change in v out is equal to the delta of i load esr of c out . the delta of i load charges or discharges the output voltage on capacitor c out . this continues until the regulator loop responds to the change in load and is able to restore v out to its original value. v out should be monitored during the step change in load for overshoot, undershoot or ringing, which may indicate a stability problem. the circuit shown in figure 1 contains external com- ponents that should provide sufficient compensation for most applications. the most demanding form of a transient that can be placed on a switching regulator is the hot switching in of loads that contain bypass or other sources of capacitance greater than 1 m f. when a discharged capacitor is placed on the load it is effectively placed in parallel with the output cap c out , and results in a rapid drop in the output voltage v out . switching regulators are not capable of supplying enough instantaneous current to prevent this from occurring. therefore, the inrush current to the load capacitors should be held below the current limit of the design. efficiency efficiency is one of the most important reasons for choosing a switching regulator. the percentile efficiency of a regulator can be determined by dividing the output power of the device by the input power and then multiplying the results by 100. efficiency losses can occur at any point in a circuit and it is important to analyze the individual losses to determine changes that would yield the most improvement. the efficiency of a circuit can be expressed as: % efficiency = 100 % C ( % l 1 + % l 2 + % l 3 . . . etc. ) l1, l2, l3, etc., are the individual losses as a percentage of the input power. in high efficiency circuits small errors result when expressing losses as a percentage of the output power.
adp1147-3.3/adp1147-5 C10C rev. 0 losses are encountered in all elements of the circuit, but the four major sources for the circuit shown in figure 1 are: 1. the adp1147 dc bias current. 2. the mosfet gate charge current. 3. the i 2 r losses. 4. the voltage drop of the schottky diode. 1. the adp1147s dc bias current is the amount of current that flows into v in of the device minus the gate charge current. with v in = 10 volts, the dc supply current to the device is typically 160 m a for a no load condition, and increases pro- portionally with load to a constant of 1.6 ma in the continu- ous mode of operation. losses due to dc bias currents increase as the input voltage v in is increased. at v in = 10 volts the dc bias losses are usually less than 1% with a load current greater than 30 ma. when very low load currents are encountered the dc bias current becomes the primary point of loss. 2. the mosfet gate charge current is due to the switching of the power mosfets gate capacitance. as the mosfets gate is switched from a low to a high and back to a low again, charge impulses dq travel from v in to ground. the current out of v in is equal to dq/dt and is usually much greater than the dc supply current. when the device is operating in the continuous mode the i gate charge is = f (q p ). typically a p-channel power mosfet with an r ds on of 135 m w will have a gate charge of 40 nc. with a 100 khz, switching frequency in the continuous mode, the i gate charge would equate to 4 ma or about a 2%C3% loss with a v in of 10 volts. it should be noted that gate charge losses increase with switching frequency or input voltage. a design requiring the highest efficiency can be obtained by using more moderate switching frequencies. 3. i 2 r loss is a result of the combined dc circuit resistance and the output load current. the primary contributors to circuit dc resistance are the mosfet, the inductor and r sense . in the continuous mode of operation the average output current is switched between the mosfet and the schottky diode and a continuous current flows through the inductor and r sense . therefore the r ds(on) of the mosfet is multiplied by the on portion of the duty cycle. the result is then combined with the resistance of the inductor and r sense . the following equations and example show how to approximate the i 2 r losses of a circuit. r ds(on) ( duty cycle ) + r inductor + r sense = r i load 2 r = p loss v out i load = p out p loss /p out 100 = % i 2 r loss . with the duty cycle = 0.5, r inductor = 0.15, r sense = 0.05 and i load = 0.5 a. the result would be a 3% i 2 r loss. the effects of i 2 r losses causes the efficiency to fall off at higher output currents. 4. at high current loads the schottky diode can be a substantial point of power loss. the diode efficiency is further reduced by the use of high input voltages. to calculate the diode loss, the load current should be multiplied by the duty cycle of the diode times the forward voltage drop of the diode. i load % duty cycle v drop = diode loss figure 6 indicates the distribution of losses versus load cur- rent in a typical adp1147 switching regulator circuit. with medium current loads the gate charge current is responsible for a substantial amount of efficiency loss. at lower loads the gate charge losses become large in comparison to the load, and result in unacceptable efficiency levels. when low load currents are encountered the adp1147 employs a power savings mode to reduce the effects of the gate loss. in the power savings mode of operation the dc supply current is the major source of loss and becomes a greater percentage as the output current decreases. losses at higher loads are primarily due to i 2 r and the schottky diode. all other variables such as capacitor esr dissipation, mosfet switching, and inductor core losses typically contribute less than 2% additional loss. circuit design example in using the design example below assumptions are as follows: v in = 5 volts v out = 3.3 volts v diode drop (v d ) = 0.4 volts i max out = 1 amp max switching frequency (f) = 100 khz. the values for r sense , c t and l can be calculated based on the above assumptions. r sense = 100 mv/1 amp = 100 m w . t off time = (1/100 khz) [1 C (3.7/5.4)] = 3.15 m s. c t = 3.15 m s /(1.3 10 4 ) = 242 pf. l = 5.1 10 5 0.1 w 242 pf 3.3 v = 41 m h. if we further assume: 1. the data is specified at +25 c. 2. mosfet max power dissipation (p p ) is limited to 250 mw. 3. mosfet thermal resistance is 50 c/w. 4. the normalized r ds(on) vs. temperature approximation ( d p ) is 0.007/ c. this results in 250 mw 50 c per watt = 12.5 c of mosfet heat rise. if the ambient temperature t a is 50 c, a junction temperature of 12.5 c +50 c, t a = 62.5 c. d p = 0.007 (62.5 c C25 c) = 0.2625 we can now determine the required r ds(on) for the mosfet: r ds ( on ) = 5(0.25)/3.3 (1) 2 (1.2625) = 300 m w the above requirements can be met with the use of a p-channel irf7204 or an si9430. when v out is short circuited the power dissipation of the schottky diode is at worst case and the dissipation can rise greatly. the following equation can be used to determine the power dissipation: p d = i sc(avg) v diode drop a 100 m w r sense resistor will yield an i sc(avg) of 1 a. with a forward diode drop of 0.4 volts a 400 milliwatt diode power dissipation results. the rms current rating needed for c in will be at least 0.5 a over the temperature range.
adp1147-3.3/adp1147-5 C11C rev. 0 to obtain optimum efficiency the required esr value of c out is 100 m w or less. the circuit should also be evaluated with the minimum input voltage. this is done to assure that the power dissipation and junction temperature of the p-channel mosfet are not ex- ceeded. at lower input voltages the operating frequency of the adp1147 decreases. this causes the p-channel mosfet to remain in conduction for longer periods of time, resulting in more power dissipation in the mosfet. the effects of v in(min) can be evaluated if we assume the foll owing: v in(min) = 4.5 v v out = 3.3 v v d = 0.4 v f min = (1/3.15 m s) (1C (3.7/4.9)) = 78 khz. p d = 3.3(0.125 w )(1 a ) 2 (1.2625 ) 4.5 = 116 mw troubleshooting hints efficiency is the primary reason for choosing the adp1147 for use in an application, and it is critical to determine that all por- tions of the circuit are functioning properly in all modes. after the design is complete the voltage waveforms on the timing capacitor, c t , at pin 2 of the device, should be compared to the waveforms in figures 19a and 19b. in the continuous mode of operation the dc voltage level of the waveform on c t should never fall below the 2 v level and it should have a 0.9 v peak-to-peak sawtooth on it (see figure 19a). in the power savings mode the sawtooth waveform on c t will decay to ground for extended periods of time (see figure 19b). during the time that the capacitor voltage is at ground the adp1147 is in the power savings or sleep mode and the qui- escent current is reduced to 160 m a typical. the ripple current in the inductor should also be monitored to determine that it is approximately the same in both modes of operation. with a higher output currents the voltage level on c t should never decay to ground as this would indicate poor grounding and or decoupling. printed wire board layout considerations the pwb layout is extremely critical for proper circuit opera- tion and the items listed below should be carefully considered (see figure 20) 1. the signal and power grounds should be separate from each other. they should be tied together only at ground pin 7 of the adp1147. the power ground should be tied to the an- ode of the schottky diode, and the (C) side of the c in capaci- tor. the connections should be made with traces that are as wide and as short as possible. the signal ground should be connected to the (C) side of capacitor c out using the same type of runs as above. 2. the sense(C) run to pin 4 of the adp1147 should be con- nected directly to the junction point of r sense and the + side of c out . 3. the sense(C) and sense(+) traces should be routed together with minimum track spacing and run lengths. the 1000 pf filter capacitor across pins 4 and 5 of the adp1147 should be located as close to the device as possible. 4. in order to supply sufficient ac current the (+) side of capaci- tor c in should be connected with wide short traces and must be located as close to the source of the p-mosfet as possible. 5. in order to supply high frequency peak currents the input deco upling capacitors should range from 0.1 m f to 1.0 m f and must be located as close to the v in pin and the ground pin 7 as possible. 6. the shutdown pin (6) is a high impedance input and it must not be allowed to float. the normal mode of operation of the device requires that this pin be pulled low.
adp1147-3.3/adp1147-5 C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c3148C8C2/98 printed in u.s.a. 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45

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